View NBC12439AMNR4G_4303328.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2009 january, 2009 ? rev. 14 1 publication order number: nbc12439/d nbc12439, nbc12439a 3.3v/5v?programmable pll synthesized clock generator 50 mhz to 800 mhz description the nbc12439 and nbc12439a are general purpose, pll based synthesized clock sources. the vco will operate over a frequency range of 400 mhz to 800 mhz. the vco frequency is sent to the n ? output divider, where it can be configured to provide division ratios of 1, 2, 4 or 8. the vco and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. output frequency steps of 16 mhz, 8 mhz, 4 mhz, or 2 mhz can be achieved using a 16 mhz crystal, depending on the output divider settings. the pll loop filter is fully integrated and does not require any external components. features ? best ? in ? class output jitter performance, 20 ps peak ? to ? peak ? 50 mhz to 800 mhz programmable differential pecl outputs ? fully integrated phase ? lock ? loop with internal loop filter ? parallel interface for programming counter and output dividers during powerup ? minimal frequency overshoot ? serial 3 ? wire programming interface ? crystal oscillator inputs 10 mhz to 20 mhz ? operating range: v cc = 3.135 v to 5.25 v ? cmos and ttl compatible control inputs ? pin and function compatible with motorola mc12439 and mpc9239 ? powerdown of pecl outputs ( 16) ? 0 c to 70 c ambient operating temperature (nbc12439) ? ? 40 c to 85 c ambient operating temperature (nbc12439a) ? pb ? free packages are available marking diagrams plcc ? 28 fn suffix case 776 nbc12439xg awlyyww 128 lqfp ? 32 fa suffix case 873a http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 17 of this data sheet. ordering information x = blank or a a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package nbc12 439x awlyywwg qfn32 mn suffix case 488am 32 1 nbc12 439x awlyyww 1 (note: microdot may be in either location)
nbc12439, nbc12439a http://onsemi.com 2 figure 1. block diagram (28 ? lead plcc) 7 ? bit m counter 2 7 ? bit sr 2 ? bit sr 3 ? bit sr 2 10 ? 20mhz s_load p_load s_data s_clock xtal1 xtal2 osc 4 5 phase detector 28 7 latch vco n (1, 2, 4, 8) latch 400 ? 800 mhz fout fout +3.3 or 5.0 v 21, 25 24 23 v cc latch test 20 +3.3 or 5.0 v pll_v cc f ref 01 27 26 01 m[6:0] 7 8 14 n[1:0] 2 17, 18 22, 19 oe 6 fref_ext 3 xtal_sel 15 1 pwr_down 2 power down table 1. output division n [1:0] output division 0 0 0 1 1 0 1 1 2 4 8 1 table 2. xtal_sel and oe input 0 1 pwr_down xtal_sel oe* f out fref_ext outputs disabled f out 16 xtal outputs enabled *when disabled, fout goes low, fout goes high.
nbc12439, nbc12439a http://onsemi.com 3 n[1] n[0] nc xtal_sel m[6] m[5] m[4] xtal1 fref_ext pwr_down pll_v cc s_load s_data s_clock figure 2. 28 ? lead plcc (top view) v cc fout fout gnd v cc gnd test xtal2 oe p_load m[0] m[1] m[2] m[3] figure 3. 32 ? lead lqfp (top view) n/c n[1] n[0] nc xtal_sel m[6] m[5] fref_ext pwr_down pll_v cc pll_v cc s_load s_data s_clock fout fout gnd v cc v cc gnd test oe p_load m[0] m[1] m[2] m[3] n/c m[4] xtal1 v cc xtal2 26 27 28 1 2 3 4 18 17 16 15 14 13 12 56 7891011 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 910111213141516 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 9 10 11 12 1314 1516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 n/c n[1] n[0] nc xtal_sel m[6] m[5] fref_ext pwr_down pll_v cc pll_v cc s_load s_data s_clock fout fout gnd v cc v cc gnd test oe p_load m[0] m[1] m[2] m[3] n/c m[4] xtal1 v cc xtal2 figure 4. 32 ? lead qfn (top view) exposed pad (ep)
nbc12439, nbc12439a http://onsemi.com 4 the following gives a brief description of the functionality of the nbc12439 and nbc12349a inputs and outputs. unless explicitly stated, all inputs are cmos/ttl compatible with either pull ? up or pulldown resistors. the pecl outputs are capable of driving two series terminated 50 transmission lines on the incident edge. table 3. pin function description pin name function description inputs xtal1, xtal2 crystal inputs these pins form an oscillator when connected to an external series ? resonant crystal. s_load* cmos/ttl serial latch input (internal pulldown resistor) this pin loads the configuration latches with the contents of the shift registers. the latches will be transparent when this signal is high; thus, the data must be stable on the high ? to ? low transition of s_load for proper operation. s_data* cmos/ttl serial data input (internal pulldown resistor) this pin acts as the data input to the serial configuration shift registers. s_clock* cmos/ttl serial clock input (internal pulldown resistor) this pin serves to clock the serial configuration shift registers. data from s_data is sampled on the rising edge. p_load ** cmos/ttl parallel latch input (internal pullup resistor) this pin loads the configuration latches with the contents of the parallel inputs .the latches will be transparent when this signal is low; therefore, the parallel data must be stable on the low ? to ? high transition of p_load for proper opera- tion. m[6:0]** cmos/ttl pll loop divider inputs (internal pullup resistor) these pins are used to configure the pll loop divider. they are sampled on the low ? to ? high transition of p_load . m[6] is the msb, m[0] is the lsb. n[1:0]** cmos/ttl output divider inputs (internal pullup resistor) these pins are used to configure the output divider modulus. they are sampled on the low ? to ? high transition of p_load . oe** cmos/ttl output enable input (internal pullup resistor) active high output enable. the enable is synchronous to eliminate possibility of runt pulse generation on the fout output. when disabled, fout goes low and fout . fref_ext* cmos/ttl input (internal pulldown resistor) this pin can be used as the pll reference xtal_sel** cmos/ttl input (internal pullup resistor) this pin selects between the crystal and the fref_ext source for the pll refer- ence signal. a high selects the crystal input. pwr_down cmos/ttl input (internal pulldown resistor) pwr_down forces the fout outputs to synchronously reduce frequency by a factor of 16. outputs fout, fout pecl differential outputs these differential, positive ? referenced ecl signals (pecl) are the outputs of the synthesizer. test cmos/ttl output the function of this output is determined by the serial configuration bits t[2:0]. power v cc positive supply for the logic the positive supply for the internal logic and output buffer of the chip, and is con- nected to +3.3 v or +5.0 v. pll_v cc positive supply for the pll this is the positive supply for the pll and is connected to +3.3 v or +5.0 v. gnd negative power supply these pins are the negative supply for the chip and are normally all connected to ground. ? exposed pad for qfn ? 32 only the exposed pad (ep) on the qfn ? 32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be at- tached to a heat ? sinking conduit. the pad is electrically connected to gnd. * when left open, these inputs will default low. ** when left open, these inputs will default high.
nbc12439, nbc12439a http://onsemi.com 5 table 4. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 150 v > 1 kv moisture sensitivity (note 1) pb pkg pb ? free pkg plcc lqfp qfn level 1 level 2 level 1 level 3 level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 2269 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 5. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive supply gnd = 0 v 6 v v i input voltage gnd = 0 v v i v cc 6 v i out output current continuous surge 50 100 ma ma t a operating temperature range nb12439 nb12439a 0 to 70 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm plcc ? 28 plcc ? 28 63.5 43.5 c/w c/w jc thermal resistance (junction ? to ? case) standard board plcc ? 28 22 to 26 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm lqfp ? 32 lqfp ? 32 80 55 c/w c/w jc thermal resistance (junction ? to ? case) standard board lqfp ? 32 12 to 17 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p qfn ? 32 12 c/w t sol wave solder pb pb ? free <3 sec @ 248 c <3 sec @ 260 c 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nbc12439, nbc12439a http://onsemi.com 6 table 6. dc characteristics (v cc = 3.3 v 5%; t a = 0 c to 70 c (nbc12439), t a = ? 40 c to 85 c (nbc12439a)) symbol characteristic condition min typ max unit v ih lvcmos/ lvttl input high voltage v cc = 3.3 v 2.0 v v il lvcmos/ lvttl input low voltage v cc = 3.3 v 0.8 v i in input current 1.0 ma v oh output high voltage test i oh = ? 0.8 ma 2.5 v v ol output low voltage test i ol = 0.8 ma 0.4 v v oh pecl output high voltage fout fout v cc = 3.3 v (notes 2, 3) 2.155 2.405 v v ol pecl output low voltage fout fout v cc = 3.3 v (notes 2, 3) 1.355 1.675 v i cc power supply current v cc pll_v cc 44 19 58 23 80 28 ma ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. f out /f out output levels will vary 1:1 with v cc variation. 3. f out /f out outputs are terminated through a 50 resistor to v cc ? 2.0 volts. table 7. dc characteristics (v cc = 5.0 v 5%; t a = 0 c to 70 c (nbc12439), t a = ? 40 c to 85 c (nbc12439a)) symbol characteristic condition min typ max min typ max min typ max unit v ih cmos/ ttl input high voltage v cc = 5.0 v 2.0 2.0 2.0 v v il cmos/ ttl input low voltage v cc = 5.0 v 0.8 0.8 0.8 v i in input current 1.0 1.0 1.0 ma v oh output high voltage test i oh = ? 0.8 ma 2.5 2.5 2.5 v v ol output low voltage test i ol = 0.8 ma 0.4 0.4 0.4 v v oh pecl output high voltage fout fout v cc = 5.0 v (notes 4, 5) 3.855 4.105 3.855 4.105 3.855 4.105 v v ol pecl output low voltage fout fout v cc = 5.0 v (notes 4, 5) 3.055 3.305 3.055 3.305 3.055 3.305 v i cc power supply current v cc pll_v cc 47 19 58 24 85 28 47 19 60 24 85 28 47 19 60 24 85 28 ma ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. f out /f out output levels will vary 1:1 with v cc variation. 5. f out /f out outputs are terminated through a 50 resistor to v cc ? 2.0 volts.
nbc12439, nbc12439a http://onsemi.com 7 table 8. ac characteristics (v cc = 3.135 v to 5.25 v 5%; t a = 0 c to 70 c (nbc12439), t a = ? 40 c to 85 c (nbc12439a)) (note 7) symbol characteristic condition min max unit f in input frequency s_clock xtal oscillator fref_ext (note 8) (note 6) ? 10 10 10 20 100 mhz f out output frequency vco (internal) f out 400 50 800 800 mhz t lock maximum pll lock time 10 ms t jitter(pd) period jitter (rms) (1 ) 50 mhz f out < 100 mhz 100 mhz f out < 800 mhz 8 5 ps t jitter(cyc ? cyc) cycle ? to ? cycle jitter (peak ? to ? peak) (8 ) 50 mhz f out < 100 mhz 100 mhz f out < 800 mhz 40 20 ps t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ? ? ? ns t h hold time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ? ? ? ns tpw min minimum pulse width s_load p_load 50 50 ? ? ns dco output duty cycle 47.5 52.5 % t r , t f output rise/fall fout 20% ? 80% 175 425 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. 10 mhz is the maximum frequency to load the feedback divide registers. s_clock can be switched at higher frequencies when use d as a test clock in test_mode 6. 7. f out /f out outputs are terminated through a 50 resistor to v cc ? 2.0 v. intern al phase detector can handle up to 100 mhz on it?s input. 8. maximum frequency on fref_ext is a function of setting the appropriate m counter value for the vco to operate within the vali d range of 400 mhz f vco 800 mhz. (see table 11) 9. see applications information section.
nbc12439, nbc12439a http://onsemi.com 8 functional description the internal oscillator uses the external quartz crystal as the basis of its frequency reference. the output of the reference oscillator is divided by 2 before being sent to the phase detector. with a 16 mhz crystal, this provides a reference frequency of 8 mhz. although this data sheet illustrates functionality only for a 16 mhz crystal, table 9, any crystal in the 10 ? 20 mhz range can be used, t able 11. the vco within the pll operates over a range of 400 to 800 mhz. its output is scaled by a divider, m divider, that is configured by either the serial or parallel interfaces. the output of this loop divider is also applied to the phase detector. the phase detector and the loop filter force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve loop lock. the output of the vco is also passed through an output divider before being sent to the pecl output driver. this n output divider is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4, or 8). this divider extends the performance of the part while providing a 50% duty cycle. the output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated into 50 to v cc ? 2.0 v. the positive reference for the output driver and the internal logic is separated from the power supply for the phase ? locked loop to minimize noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[6:0] and n[1:0] inputs to configure the internal counters. normally upon system reset, the p_load input is held low until sometime after power becomes valid. on the low ? to ? high transition of p_load , the parallel inputs are captured. the parallel interface has priority over the serial interface. internal pullup resistors are provided on the m[6:0] and n[1:0] inputs to reduce component count in the application of the chip. the serial interface logic is implemented with a fourteen bit shift register scheme. the register shifts once per rising edge of the s_clock input. the serial input s_data must meet setup and hold timing as specified in the ac characteristics section of this document. with p_load held high, the configuration latches will capture the value of the shift register on the high ? to ? low edge of the s_load input. see the programming section for more information. the test output reflects various internal node values and is controlled by the t[2:0] bits in the serial data stream. see the programming section for more information. table 9. programming vco frequency function table with 16 mhz crystal 400 ? 752
nbc12439, nbc12439a http://onsemi.com 9 programming interface programming the nbc12439 and nbc12439a is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. the output frequency can by represented by this formula: f out (f xtal or fref_ext 2) 2m n (eq. 1) this can be simplified to: f out (f xtal or fref_ext) m n (eq. 2) where f xtal is the crystal frequency, m is the loop divider modulus, and n is the output divider modulus. note that it is possible to select values of m such that the pll is unable to achieve loop lock. to avoid this, always make sure that m is selected to be 25 m 50 for a 16 mhz input reference. see table 11. assuming that a 16 mhz reference frequency is used the above equation reduces to: f out 16m n (eq. 3) substituting the four values for n (1, 2, 4, 8) yields: table 10. programmable output divider function table 1 1 16 ? 800 2 8 ? 400 4 4 ? 200 8 2 ? 100 the user can identify the pr oper m and n values for the desired frequency from the a bove equations. the four output frequency ranges established by n are 400 ? 800 mhz, 200 ? 400 mhz, 100 ? 200 mhz and 50 ? 100 mhz, respectively. from these ranges, the user will establish the value of n required. the value of m can then be calculated based on equation 1. for exampl e, if an output frequency of 384 mhz was desired, the following steps would be taken to identify the appropriate m and n values. 384 mhz falls within the frequency range set by an n value of 2; thus, n [1:0] = 00. for n = 2, f out = 8m and m = f out 8. therefore, m = 384 8 = 48, so m[6:0] = 0110000. following this same procedure, a user can generate a selected frequency. the size of the programmable frequency steps of f out will be equal to f xtal n. for input reference frequencies other than 16 mhz, see table 11, which shows the usable vco frequency and m divider range. the input frequency and the selection of the feedback divider m is limited by the vco frequency range and fxtal. m must be configured to match the vco frequency range of 400 to 800 mhz in order to achieve stable pll operation. m min f vcomin f xtal and (eq. 4) m max f vcomax f xtal (eq. 5) the value for m falls within the constraints set for pll stability. if the value for m fell outside of the valid range, a different n value would be selected to move m in the appropriate direction. the m and n counters can be loaded either through a parallel or serial interface. the parallel interface is controlled via the p_load signal such that a low to high transition will latch the information present on the m[6:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low, the input latches will be transparent and any changes on the m[6:0] and n[1:0] inputs will affect the fout output pair. to use the serial port, the s_clock signal samples the information on the s_data line and loads it into a 12 bit shift register. note that the p_load signal must be high for the serial load operation to function. the test register is loaded with the first three bits, the n register with the next two, and the m register with the final nine bits of the data stream on the s_data input. for each register, the most significant bit is loaded first (t2, n1, and m6). the high to low transition on the s_load input will latch the new divide values into the counters. a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. figures 5 and 6 illustrate the timing diagram for both a parallel and a serial load of the device synthesizer. m[6:0] and n[1:0] are normally specified after power ? up through the parallel interface, and then possibly, fine tuned again through the serial interface. this approach allows the application to ramp up at one frequency and then change or fine ? tune the clock as the ability to control the serial interface becomes available. the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable through the parallel interface. the t2, t1, and t0 control bits are preset to ?000? when p_load is low so that the pecl fout outputs are as jitter ? free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair. in normal operations, jitter specifications are only guaranteed if the test output is static. the serial configuration port can be used to select one of the alternate functions for this pin.
nbc12439, nbc12439a http://onsemi.com 10 table 11. frequency operating range 1 2 4 8 20 0010100 400 21 0010101 420 22 0010110 440 23 0010111 414 460 24 0011000 432 480 25 0011001 400 450 500 400 200 100 50 26 0011010 416 468 520 416 208 104 52 27 0011011 432 486 540 432 216 108 54 28 0011100 448 504 560 448 224 112 56 29 0011101 406 464 522 580 464 232 116 58 30 0011110 420 480 540 600 480 240 120 60 31 0011111 434 496 558 620 496 248 124 62 32 0100000 448 512 576 640 512 256 128 64 33 0100001 462 528 594 660 528 264 132 66 34 0100010 408 476 544 612 680 544 272 136 68 35 0100011 420 490 560 630 700 560 280 140 70 36 0100100 432 504 576 648 720 576 288 144 72 37 0100101 444 518 592 666 740 592 296 148 74 38 0100110 456 532 608 684 760 608 304 152 76 39 0100111 468 546 624 702 780 624 312 156 78 40 0101000 400 480 560 640 720 800 640 320 160 80 41 0101001 410 492 574 656 738 656 328 164 82 42 0101010 420 504 588 672 756 672 336 168 84 43 0101011 430 516 602 688 774 688 344 172 86 44 0101100 440 528 616 704 792 704 352 176 88 45 0101101 450 540 630 720 720 360 180 90 46 0101110 460 552 644 736 736 368 184 92 47 0101111 470 564 658 752 752 376 188 94 48 0110000 480 576 672 768 768 384 192 96 49 0110001 490 588 686 784 784 392 196 98 50 0110010 500 600 700 800 800 400 200 100 51 0110011 510 612 714 52 0110100 520 624 728 53 0110101 530 636 742 54 0110110 540 648 756 55 0110111 550 660 770 56 0111000 560 672 784 57 0111001 570 684 798 58 0111010 580 696 59 0111011 590 708 60 0111100 600 720 61 0111101 610 732 62 0111110 620 744 63 0111111 630 756 64 1000000 640 768 65 1000001 650 780 66 1000010 660 792 67 1000011 670 68 1000100 680 69 1000101 690 70 1000110 700 71 1000111 710 72 1001000 720 73 1001001 730 74 1001010 740 75 1001011 750 76 1001100 760 77 1001101 770 78 1001110 780 79 1001111 790 80 1010000 800
nbc12439, nbc12439a http://onsemi.com 11 most of the signals available on the test output pin are useful only for performance verification of the device itself. however, the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110, the device is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the fout differential pair and the m counter drives the test output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving fout directly gives the user more control on the test clocks sent through the clock tree. figure 7 shows the functional setup of the pll bypass mode. because the s_clock is a cmos level the input frequency is limited to 250 mhz or less. this means the fastest the fout pin can be toggled via the s_clock is 250 mhz as the minimum divide ratio of the n counter is 1. note that the m counter output on the test output will not be a 50% duty cycle due to the way the divider is implemented. t2 t1 t0 test output 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 shift register out high fref m counter out fout low pll bypass fout 4 figure 5. parallel interface timing diagram m[8:0] n[1:0] p_load figure 6. serial interface timing diagram s_clock s_data s_load last bit c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 t2 t1 t0 n1 n0 m6 m5 m4 m3 m2 m1 m0 first bit ???? ???? ???? ???? figure 7. serial test clock block diagram ? t2=t1=1, t0=0: test mode ? sclock is selected, mcnt is on test output, sclock n is on fout pin. pload acts as reset for test pin latch. when latch reset, t2 data is shifted out test pin. fdiv4 mcnt low f out mcnt fref high test mux 7 0 test f out (via enable gate) n (1, 2, 4, 8) 0 1 pll 12430 latch reset pload m counter sload t0 t1 t2 vco_clk shift reg 14 ? bit decode sdata sclock mcnt fref_ext
nbc12439, nbc12439a http://onsemi.com 12 applications information using the on ? board crystal oscillator the nbc12439 and nbc12439a feature a fully integrated on ? board crystal oscillator to minimize system implementation costs. the oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. the series resonant design provides better stability and eliminates the need for large load capacitors. the oscillator is totally self contained so that the only external component required is the crystal per figure 8 (do not use cyrstal load caps). as the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the device as possible to avoid any board level parasitics. to facilitate co ? location, surface mount crystals are recommended, but not required. because the series resonant design is affected by capacitive loading on the crystal terminals, loading variation introduced by crystals from different vendors could be a potential issue. for crystals with a higher shunt capacitance, it may be required to place a resistance, optional r shunt , across the terminals to suppress the third harmonic. although typically not required, it is a good idea to layout the pcb with the provision of adding this external resistor. the resistor value will typically be between 500 and 1 k . the oscillator circuit is a series resonant circuit and thus, for optimum performance, a series resonant crystal should be used. unfortunately, most crystals are characterized in a parallel resonant mode. fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. the difference is purely in the way the devices are characterized. as a result, a parallel resonant crystal can be used with the device with only a minor error in the desired frequency. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified (a few hundred ppm translates to khz inaccuracy). table 12 below specifies the performance requirements of the crystals to be used with the device. figure 8. crystal application table 12. crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75 ppm at 25 c frequency/temperature stability 150 ppm 0 to 70 c operating range 0 to 70 c shunt capacitance 5 ? 7 pf equivalent series resistance (esr) 50 to 80 correlation drive level 100 w aging 5 ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion. power supply filtering the nbc12439 and nbc12439a are mixed analog/digital products and as such, exhibit some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the nbc12439 and nbc1239a provide separate power supplies for the digital circuitry (v cc ) and the internal pll (pll_v cc ) of the device. the purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase ? locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient. however, in a digital system environment where it is more dif ficult to minimize noise on the power supplies, a second level of isolation may be required. the simplest form of isolation is a power supply filter on the pll_v cc pin for the nbc12439 and nbc12349a. figure 9 illustrates a typical power supply filter scheme. the nbc12439 and nbc12439a are most susceptible to noise with spectral content in the 1 khz to 1 mhz range. therefore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the pll_v cc pin of the nbc12439 and nbc12439a. from the data sheet, the pll_v cc current (the current sourced through the pll_v cc pin) is typically 23 ma (28 ma maximum). assuming that a minimum of 2.8 v must be maintained on the pll_v cc pin, very little dc voltage drop can be tolerated when a 3.3 v v cc supply is used. the resistor shown in figure 9 must have a resistance of 10 ? 15 to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 khz. as the noise frequency crosses the series resonant point of an individual capacitor, it?s overall
nbc12439, nbc12439a http://onsemi.com 13 impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. figure 9. power supply filter pll_v cc v cc nbc12439 nbc12439a 0.01 f 22 f l=1000 h r=15 0.01 f 3.3 v or 5.0 v r s = 10 ? 15 3.3 v or 5.0 v a higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. figure 9 shows a 1000 h choke. this value choke will show a significant impedance at 10 khz frequencies and above. because of the current draw and the voltage that must be maintained on the pll_v cc pin, a low dc resistance inductor is required (less than 15 ). generally, the resistor/capacitor filter will be cheaper, easier to implement, and provide an adequate level of supply filtering. the nbc12439 and nbc12439a provide sub ? nanosecond output edge rates and therefore a good power supply bypassing scheme is a must. figure 10 shows a representative board layout for the nbc12439. there exists many different potential board layouts and the one pictured is but one. the important aspect of the layout in figure 10 is the low impedance connections between v cc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the nbc12439 and nbc12439a outputs. it is imperative that low inductance chip capacitors are used. it is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. figure 10. pcb board layout for (plcc ? 28) c2 1 c3 r1 xtal c1 c1 r1 = 10 ? 15 c1 = 0.01 f c2 = 22 f c3 = 0.1 f note the dotted lines circling the crystal oscillator connection to the device. the os cillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. it is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on ? board oscillator. note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. although the nbc12439 and nbc12439a have several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll), there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise ? related problems in most designs. jitter performance jitter is a common parameter associated with clock generation and distribution. clock jitter can be defined as the deviation in a clock?s output transition from its ideal position. cycle ? to ? cycle jitter (short ? term) is the period variation between adjacent periods over a defined number of observed cycles. the number of cycles observed is
nbc12439, nbc12439a http://onsemi.com 14 application dependent but the jedec specification is 1000 cycles. see figure 11. figure 11. cycle ? to ? cycle jitter t jitter(cycle ? cycle) = t 1 ? t 0 t 0 t 1 random peak ? to ? peak jitter is the dif ference between the highest and lowest acquired value and is represented as the width of the gaussian base. see figure 12. figure 12. random peak ? to ? peak and rms jitter time* typical gaussian distribution rms or one sigma jitter jitter amplitude peak ? to ? peak jitter (8 ) *1,000 ? 10,000 cycles there are different ways to measure jitter and often they are confused with one another. an earlier method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period ? to ? period or cycle ? to ? cycle. if the scope is set up to trigger on every rising or falling edge, set to infinite persistence mode and allowed to trace suf ficient cycles, it is possible to determine the maximum and minimum periods of the timing signal. digital scopes can accumulate a large number of cycles, create a histogram of the edge placements and record peak ? to ? peak as well as standard deviations of the jitter. care must be taken that the measured edge is the edge immediately following the trigger edge. these scopes can also store a finite number of period durations and post ? processing software can analyze the data to find the maximum and minimum periods. recent hardware and software developments have resulted in advanced jitter measurement techniques. the tektronix tds ? series oscilloscopes have superb jitter analysis capabilities on non ? contiguous clocks with their histogram and statistics capabilities. the tektronix tdsjit2/3 jitter analysis software provides many key timing parameter measurements and will extend that capability by making jitter measurements on contiguous clock and data cycles from single ? shot acquisitions. m1 by amherst was used as well and both test methods correlated. this test process can be correlated to earlier test methods and are more accurate. all of the jitter data reported on the nbc12439 and nbc12439a was collected in this manner. figure 13 shows the rms jitter performance as a function of the vco frequency range. the general trend is that as the vco frequency is increased, the rms output jitter will decrease. figure 14 illustrates the rms jitter performance versus the output frequency. note the jitter is a function of both the output frequency as well as the vco frequency. however, the vco frequency shows a much stronger dependence. long ? term period jitter is the maximum jitter observed at the end of a period? s edge when compared to the position of the perfect reference clock?s edge and is specified by the number of cycles over which the jitter is measured. the number of cycles used to look for the maximum jitter varies by application but the jedec spec is 10,000 observed cycles. the nbc12439 and nbc12439a exhibit long term and cycle ? to ? cycle jitter, which rivals that of saw based oscillators. this jitter performance comes with the added flexibility associated with a synthesizer over a fixed frequency oscillator. the jitter data presented should provide users with enough information to determine the effect on their overall timing budget. the jitter performance meets the needs of most system designs while adding the flexibility of frequency mar gining and field upgrades. these features are not available with a fixed frequency saw oscillator.
nbc12439, nbc12439a http://onsemi.com 15 figure 13. cycle ? to ? cycle rms jitter vs. vco frequency vco frequency (mhz) 400 500 600 700 800 25 20 15 10 5 0 rms jitter (ps) n = 1 n = 8 n = 2 n = 4 figure 14. cycle ? to ? cycle rms jitter vs. output frequency 25 20 15 10 5 0 rms jitter (ps) 800 700 600 500 400 300 200 100 output frequency (mhz)
nbc12439, nbc12439a http://onsemi.com 16 t set ? up t hold s_clock s_data figure 15. setup and hold t set ? up t hold s_load s_data figure 16. setup and hold t set ? up t hold p_ load m[6:0] figure 17. setup and hold t period pulse width f out f out figure 18. output duty cycle n[1:0] dco pw period
nbc12439, nbc12439a http://onsemi.com 17 figure 19. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device d f out d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v f out ordering information device package shipping ? nbc12439fa lqfp ? 32 250 units / tray nbc12439fag lqfp ? 32 (pb ? free) 250 units / tray nbc12439far2 lqfp ? 32 2000 / tape & reel nbc12439far2g lqfp ? 32 (pb ? free) 2000 / tape & reel nbc12439fn plcc ? 28 37 units / rail nbc12439fng plcc ? 28 (pb ? free) 37 units / rail nbc12439fnr2 plcc ? 28 500 / tape & reel nbc12439fnr2g plcc ? 28 (pb ? free) 500 / tape & reel nbc12439afa lqfp ? 32 250 units / tray nbc12439afag lqfp ? 32 (pb ? free) 250 units / tray nbc12439afar2 lqfp ? 32 2000 / tape & reel nbc12439afar2g lqfp ? 32 (pb ? free) 2000 / tape & reel nbc12439afn plcc ? 28 37 units / rail nbc12439afng plcc ? 28 (pb ? free) 37 units / rail nbc12439afnr2 plcc ? 28 500 / tape & reel nbc12439afnr2g plcc ? 28 (pb ? free) 500 / tape & reel nbc12439amng qfn ? 32 (pb ? free) 74 units / rail NBC12439AMNR4G qfn ? 32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nbc12439, nbc12439a http://onsemi.com 18 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
nbc12439, nbc12439a http://onsemi.com 19 package dimensions 28 lead pllc case 776 ? 02 issue f ? n ? ? m ? ? l ? v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t ? t ? b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view d ? d s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.021 0.33 0.53 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
nbc12439, nbc12439a http://onsemi.com 20 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ? t ? ? z ? ? u ? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t-u m 0.20 (0.008) z ac 32 lead lqfp case 873a ? 02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
nbc12439, nbc12439a http://onsemi.com 21 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dimensions: millimeters 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nbc12439/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

▲Up To Search▲

Price & Availability of NBC12439AMNR4G

	To Download NBC12439AMNR4G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .